fdc6506p fdc6506p rev. c fdc6506p dual p-channel logic level powertrench ? mosfet february 1999 ? 1999 fairchild semiconductor corporation absolute maximum ratings t a = 25c unless otherwise noted symbol parameter ratings units v dss drain-source voltage -30 v v gss gate-source voltage 20 v i d drain current - continuous (note 1a) -1.8 a - pulsed -10 p d power dissipation for single operation (note 1a) 0.96 w (note 1b) 0.9 (note 1c) 0.7 t j , t stg operating and storage junction temperature range -55 to +150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 130 c/w r q jc thermal resistance, junction-to-case (note 1) 60 c/w package outlines and ordering information device marking device reel size tape width quantity . 506 fdc6506p 7 8mm 3000 units 5 6 4 2 3 1 general description these p-channel logic level mosfets are produced using fairchild semiconductor's advanced powertrench process that has been especially tailored to minimize on-state resistance and yet maintain low gate charge for superior switching performance. these devices have been designed to offer exceptional power dissipation in a very small footprint for applications where the bigger more expensive so-8 and tssop-8 packages are impractical. applications ? load switch ? battery protection ? power management features ? -1.8 a, -30 v. r ds(on) = 0.170 w @ v gs = -10 v r ds(on) = 0.280 w @ v gs = -4.5 v ? low gate charge (2.3nc typical). ? fast switching speed. ? high performance trench technology for extremely low r ds(on) . ? supersot tm -6 package: small footprint (72% smaller than standard so-8); low profile (1mm thick). d1 s2 g1 d2 s1 g2 supersot -6 tm
fdc6506p fdc6506p rev. c a) 130 c/w when mounted on a 0.125 in 2 pad of 2 oz. copper. b) 140 c/w when mounted on a 0.005 in 2 pad of 2 oz. copper. c) 180 c/w when mounted on a 0.0015 in 2 pad of 2 oz. copper. notes: 1. r q ja is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mou nting surface of the drain pins. r q jc is guaranteed by design while r q ja is determined by the user's board design.both devices are assumed to be operating and sharing the dissipated heat energy equally. scale 1 : 1 on letter size paper 2. pulse test: pulse width 300 m s, duty cycle 2.0% electrical characteristics t a = 25c unless otherwise noted s y mbol parameter test conditions min t yp max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = -250 m a-30 v d bv dss d t j breakdown voltage temperature coefficient i d = -250 m a , referenced to 25 c-20 mv/ c i dss zero gate voltage drain current v ds = -24 v, v gs = 0 v -1 m a i gssf gate-body leakage current, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate-body leakage current, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = -250 m a-1-1.8-3v d v gs(th) d t j gate threshold voltage temperature coefficient i d = -250 m a , referenced to 25 c4 mv/ c r ds(on) static drain-source on-resistance v gs = -10 v, i d = -1.8 a v gs = -10 v, i d = -1.8 a @125 c v gs = -4.5 v, i d = -1.4 a 0.14 0.20 0.22 0.17 0.27 0.28 w i d(on) on-state drain current v gs = -10 v, v ds = - 5 v -10 a g fs forward transconductance v ds = -5 v, i d = -1.8 a 3 s dynamic characteristics c iss input capacitance 190 pf c oss output capacitance 70 pf c rss reverse transfer capacitance v ds = -15 v, v gs = 0 v, f = 1.0 mhz 30 pf switching characteristics (note 2) t d(on) turn-on delay time 7 14 ns t r turn-on rise time 8 16 ns t d(off) turn-off delay time 14 25 ns t f turn-off fall time v dd = -15 v, i d = -1 a, v gs = -4.5 v, r gen = 6 w 26ns q g total gate charge 2.3 3.5 nc q gs gate-source charge 1 nc q gd gate-drain charge v ds = -5 v, i d = -1.8 a, v gs = -10 v 0.8 nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -0.8 a v sd drain-source diode forward voltage v gs = 0 v, i s = -0.8 a (note 2) -0.8 -1.2 v
fdc6506p fdc6506p rev. c typical characteristics figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d =-1.8a v gs =-10v 0 2 4 6 8 10 012345 -v ds , drain to source voltage (v) -i d , drain current (a) v gs =-10v -7.0v -5.5v -4.5v -4.0v -3.5v -3.0v 0.5 1 1.5 2 2.5 0246810 -i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs =-4.0v -4.5v -5.0v -6.0v -7.0v -10v 0 1 2 3 4 12345 -v gs , gate to source voltage (v) -i d , drain current (a) v ds =-5v t j =-55 o c 25 o c 125 o 0.001 0.01 0.1 1 10 0 0.3 0.6 0.9 1.2 1.5 -v sd , body diode voltage (v) -i s , reverse drain current (a) v gs =0 t j =125 o c 25 o c -55 o c 0.1 0.2 0.3 0.4 0.5 2345678910 -v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) t j =125 o c 25 o c i d =-1.0a
fdc6506p fdc6506p rev. c typical characteristics (continued) figure 7. gate-charge characteristics. figure 8. capacitance characteristics. figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1c. transient themal response will change depending on the circuit board design. 0.0001 0.001 0.01 0.1 1 10 100 300 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 r(t), normalized effective duty cycle, d = t / t 1 2 t - t = p * r (t) q ja a j p(pk) t 1 t 2 r (t) = r(t) * r r = 180 c/w q ja q ja q ja 0.01 0.1 1 10 100 300 0 1 2 3 4 5 single pulse time (sec) power (w) single pulse r =180c/w t = 25c q ja a 0.1 0.2 0.5 1 2 5 10 20 50 0.01 0.03 0.1 0.3 1 3 10 30 -v , drain-source voltage (v) -i , drain current (a) rds(on) limit d ds v = -10v single pulse r = 180c/w t = 25c q ja gs a dc 1s 100ms 10ms 1ms 100us 0 2 4 6 8 10 01234 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = -1.8a v ds =-5.0v - 10v -15v 0 60 120 180 240 300 0 6 12 18 24 30 -v ds , drain to source voltage (v) capacitance (pf) c iss c oss c rss f=1mhz v gs =0v
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